Espressif Systems /ESP32-P4 /H264_DMA /IN_ETM_CONF_CH0

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Interpret as IN_ETM_CONF_CH0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IN_ETM_EN_CH0)IN_ETM_EN_CH0 0 (IN_ETM_LOOP_EN_CH0)IN_ETM_LOOP_EN_CH0 0IN_DSCR_TASK_MAK_CH0

Description

RX CH0 ETM config register

Fields

IN_ETM_EN_CH0

Set this bit to 1 to enable ETM task function

IN_ETM_LOOP_EN_CH0

when this bit is 1, dscr can be processed after receiving a task

IN_DSCR_TASK_MAK_CH0

ETM dscr_ready maximum cache numbers

Links

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